1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a multimode data buffer and a method for controlling propagation time delay.
2. Description of the Related Art
To improve system performances, innovations in the design of semiconductor memory devices in general, and the design of dynamic random access memories (DRAMs) in particular, continue to focus on higher integration and higher speed operation. That is, DRAMs capable of processing more data at higher speed are desired. For higher speed operations, DRAMs synchronized with a system clock have been developed. This synchronous feature of DRAMs has increased data transmission speeds.
However, since a data input/output operation in a synchronous DRAM should be performed in a cycle of a system clock, there is a limit to increasing the bandwidth between the synchronous DRAM and a DRAM controller, that is, the amount of data which is input/output from a memory device in a unit time is limited. In order to increase data transmission speed, dual data rate (DDR) synchronous DRAMs in which data is input/output synchronized both with the rising edge and falling edge of a clock have been developed.
In general, a DDR synchronous DRAM uses a data strobe signal when the DRAM receives data from a memory controller or sends data to the memory controller. For example, in a data receiving operation, the DDR synchronous DRAM receives data with a data strobe signal from the memory controller. Also, in a data outputting operation, the DDR synchronous DRAM outputs data with a data strobe signal to the memory controller.
In high speed semiconductor memory devices such as DDR synchronous DRAMs, a single mode (SM)-type input buffer, which compares a data strobe signal with a reference voltage, is used as a data strobe input buffer. However, in a DDR synchronous DRAM having an SM-type data strobe signal input buffer, a data setup/hold time margin may be degraded if noise is included in a data strobe signal or reference voltage.
In order to compensate for this problem, a dual mode (DM)-type data strobe signal input buffer which compares a data strobe signal with the inverse signal of the data strobe signal instead of reference voltage has been introduced.
Since an output signal is determined at the cross point of the two signals, that is, the data strobe signal and an inverse of the data strobe signal, in the DM-type data strobe signal input buffer, noise immunity improves.
Also, more recently, in order to satisfy demands of a variety of users, an SM/DM dual-use data strobe signal input buffer has been developed. In an SM/DM dual-use data strobe signal input buffer, propagation delay time from an input terminal to an output terminal should be substantially the same both in the single mode (SM) and in the dual mode (DM). However, since the gain of a differential amplifier in the single mode is different from the gain in the dual mode, the propagation delay time in the single mode is different from the propagation delay time in the dual mode.
FIG. 1 illustrates waveforms produced in accordance with the prior art. As shown in FIG. 1, propagation delay time of the differential output signal (DS) in the SM mode is much greater than in the DM mode. Outputting the differential output signal (DS) at a different time in the SM mode and the DM mode degrades the uniformity of both the data setup time (tDS) and the data hold time (tDH) as illustrated in FIG. 1. The difference in the propagation delay time may cause a difference in the setup/hold timing in each mode such that a data setup/hold margin is degraded.
Exemplary embodiments of the present invention are directed to a data buffer, which operates in a multiple modes, such as a data strobe input buffer or a data input buffer, each of which may operate a single mode (SM) and a dual mode (DM) and where a mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. The signal may be supplied by a number of sources, such as an internal mode register set (MRS), a fuse circuit, or a bonding pad circuit.
Exemplary embodiments of the present invention are also directed to a data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin.
Exemplary embodiments of the present invention are also directed to a semiconductor memory device including one or more of the data buffers described above.
In addition, exemplary embodiments of the present invention are directed to a method for controlling propagation delay time which can improve a data setup/hold margin in a SM/DM dual-use data buffer.
Exemplary embodiments of the present invention are also directed to a data buffer including a differential amplifier circuit including at least two switches for passing an inverse data signal or a reference voltage, respectively, depending on a level of a control signal, and a differential amplifier for receiving a data signal, and either the inverse data signal or the reference voltage and outputting at least two different differentially amplified signals.
In exemplary embodiments of the present invention, the data buffer is a data strobe input buffer, the inverse data signal is an inverse data strobe signal, and the data signal is a data strobe signal.
In exemplary embodiments of the present invention, the data strobe input buffer is operable in both a single mode and a dual mode, wherein in said single mode, the reference voltage is applied to a first of the at least two switches and the level of the control signal is a first logic state and in said dual mode, the inverse data strobe signal is provided to a second of the at least two switches 212 and the level of the control signal is a second logic state.
In exemplary embodiments of the present invention, the data strobe input buffer is part of a semiconductor memory device. In exemplary embodiments of the present invention, the semiconductor memory device also includes a control circuit for outputting the control signal to the data strobe input buffer.
In exemplary embodiments of the present invention, the control circuit includes a mode register set for receiving an external command and an address and generating the control signal, wherein a level of the control signal determines a mode of the semiconductor memory device.
In exemplary embodiments of the present invention, the control circuit includes a fuse circuit including a fuse, wherein a state of the fuse determines a level of the control signal.
In exemplary embodiments of the present invention, the control circuit includes a bonding pad circuit, wherein a connection to Vcc or ground determines a level of the control signal.
In exemplary embodiments of the present invention, the differential amplifier unit includes a single differential amplifier.
In exemplary embodiments of the present invention, the semiconductor memory device further includes a compensating circuit for compensating one of the inverse data strobe signal, the reference voltage, or the data strobe signal or one of the at least two different differentially amplified signals so that each of at least two differential output signals have substantially the same delay time.
In exemplary embodiments of the present invention, the compensating circuit includes a delay circuit for receiving the differentially amplified signal from said differential amplifier circuit, said delay circuit including a delay for delaying the differentially amplified signal, at least two additional switches for passing the differentially amplified signal or the delayed differentially amplified signal, as one of the at least two differential output signals, depending on the level of the control signal.
In exemplary embodiments of the present invention, the compensating circuit includes a dummy load applied to one of the inverse data strobe signal, the reference voltage, or the data strobe signal.
In exemplary embodiments of the present invention, the differential amplifier unit includes at least two differential amplifiers.
In exemplary embodiments of the present invention, a gain of a first of the at least two differential amplifiers is substantially different from a gain of a second of the at least two differential amplifiers so that each of at least two differential output signals have substantially the same delay time.
In exemplary embodiments of the present invention, a gain of a first of the at least two differential amplifiers is substantially the same as a gain of a second of the at least two differential amplifiers.
In exemplary embodiments of the present invention, the semiconductor memory device further includes a compensating circuit for compensating one of the inverse data strobe signal, the reference voltage, or the data strobe signal or one of the at least two different differentially amplified signals so that each of at least two differential output signals have substantially the same delay time.
In exemplary embodiments of the present invention, the compensating circuit includes a delay circuit for receiving the differentially amplified signal from said differential amplifier circuit, said delay circuit including a delay for delaying the differentially amplified signal, at least two additional switches for passing the differentially amplified signal or the delayed differentially amplified signal, as one of the at least two differential output signals, depending on the level of the control signal.
In exemplary embodiments of the present invention, the compensating circuit includes a dummy load applied to one of the inverse data strobe signal, the reference voltage, or the data strobe signal.
In exemplary embodiments of the present invention, the semiconductor memory device further includes data input buffer for receiving a data signal and a reference voltage and outputting a data input signal, a control circuit for outputting the control signal to the data strobe input buffer, and a data write circuit for receiving the data input signal from said data input buffer and the writing even number data of the data input signal into a first latch in response to a rising edge of the output data signal and writing odd number data of the data input signal into a second latch in response to a falling edge of the output data strobe signal.
In exemplary embodiments of the present invention, the first latch includes a plurality of latches and a plurality of switches, arranged alternatively. In exemplary embodiments of the present invention, the plurality of switches are arranged to be triggered on the leading and falling edge of an inverse of the differential output signal.
In exemplary embodiments of the present invention, a first switch receives the even number data of the output signal of the data input buffer and passes the even number data of the output signal to a first of the plurality of latches.
In exemplary embodiments of the present invention, the second latch including a plurality of latches and a plurality of switches, arranged alternatively.
In exemplary embodiments of the present invention, the plurality of switches are arranged to be triggered on the leading and falling edge of an inverse of the differential output signal.
In exemplary embodiments of the present invention, a first switch receives the odd number data of the output signal of the data input buffer and passes the odd number data of the output signal to a first of the plurality of latches.
In exemplary embodiments of the present invention, the data buffer is a data input buffer instead of, or in addition to, a data strobe buffer.
In exemplary embodiments of the present invention, the semiconductor memory device further includes a data strobe input buffer for receiving an inverse data signal or a reference voltage, respectively, depending on a level of a control signal, and outputting at least two differential output signals, a control circuit for outputting the control signal to said data strobe input buffer, and a data write circuit for receiving the data input signal from the data input buffer and the writing even number data of the data input signal into a first latch in response to a rising edge of the output data signal and writing odd number data of the data input signal into a second latch in response to a falling edge of the output data strobe signal.
Exemplary embodiments of the present invention are also directed to a method of controlling propagation delay time of a semiconductor memory, including receiving an inverse data signal or a reference voltage, respectively, depending on a level of a control signal, receiving a data signal and either the inverse data signal or the reference voltage, and amplifying and outputting at least two different differentially amplified signals.
In exemplary embodiments of the method of the present invention, the inverse data signal is an inverse data strobe signal and the data signal is a data strobe signal.
In exemplary embodiments of the method of the present invention, in a single mode, the reference voltage is received and a level of the control signal is a first logic state and in a dual mode, the inverse data strobe signal is received and the level of the control signal is a second logic state.
In exemplary embodiments of the method of the present invention, the control signal is received from an external source.
In exemplary embodiments of the method of the present invention, the method also includes receiving an external command and an address and generating the control signal, wherein a level of the control signal determines an operation mode of the semiconductor memory.
In exemplary embodiments of the method of the present invention, a state of a fuse determines a level of the control signal.
In exemplary embodiments of the method of the present invention, a connection to Vcc or ground via a bonding pad determines a level of the control signal.
In exemplary embodiments of the method of the present invention, the amplifying is performed by a single differential amplifier.
In exemplary embodiments of the method of the present invention, the method further comprises compensating one of the inverse data strobe signal, the reference voltage, or the data strobe signal or one of the at least two different differentially amplified signals so that each of at least two differential output signals have substantially the same delay time.
In exemplary embodiments of the method of the present invention, the compensating includes receiving the differentially amplified signal and delaying the differentially amplified signal, and outputting the differentially amplified signal or the delayed differentially amplified signal, as one of the at least two differential output signals, depending on the level of the control signal.
In exemplary embodiments of the method of the present invention, the compensating is performed with a dummy load applied to one of the inverse data strobe signal, the reference voltage, or the data strobe signal.
In exemplary embodiments of the method of the present invention, the amplifying is performed by at least two differential amplifiers.
In exemplary embodiments of the method of the present invention, a gain of a first of the at least two differential amplifiers is substantially different from a gain of a second of the at least two differential amplifiers so that each of at least two differential output signals have substantially the same delay time.
In exemplary embodiments of the method of the present invention, a gain of a first of the at least two differential amplifiers is substantially the same as a gain of a second of the at least two differential amplifiers.
In exemplary embodiments of the method of the present invention, the method further comprises compensating one of the inverse data strobe signal, the reference voltage, or the data strobe signal or one of the at least two different differentially amplified signals so that each of at least two differential output signals have substantially the same delay time.
In exemplary embodiments of the method of the present invention, the compensating includes receiving the differentially amplified signal, delaying the differentially amplified signal, and outputting the differentially amplified signal or the delayed differentially amplified signal, as one of the at least two differential output signals, depending on the level of the control signal.
In exemplary embodiments of the method of the present invention, the compensating is performed with a dummy load applied to one of the inverse data strobe signal, the reference voltage, or the data strobe signal.
In exemplary embodiments of the method of the present invention, the method further includes receiving a data signal and a reference voltage and outputting a data input signal, outputting the control signal, and receiving the data input signal and the writing even number data of the data input signal into a first latch in response to a rising edge of the output data signal and writing odd number data of the data input signal into a second latch in response to a falling edge of the output data strobe signal.
In exemplary embodiments of the method of the present invention, the first latch includes a plurality of latches and a plurality of switches, arranged alternatively.
In exemplary embodiments of the method of the present invention, the plurality of switches are arranged to be triggered on the leading and falling edge of an inverse of the differential output signal.
In exemplary embodiments of the method of the present invention, a first switch receives the even number data of the output signal and passes the even number data of the output signal to a first of the plurality of latches.
In exemplary embodiments of the method of the present invention, the second latch includes a plurality of latches and a plurality of switches, arranged alternatively.
In exemplary embodiments of the method of the present invention, the plurality of switches are arranged to be triggered on the leading and falling edge of an inverse of the differential output signal.
In exemplary embodiments of the method of the present invention, a first switch receives the odd number data of the output signal and passes the odd number data of the output signal to a first of the plurality of latches.
In exemplary embodiments of the method of the present invention, the data buffer is a data input buffer instead of, or in addition to, a data strobe buffer.
In exemplary embodiments of the method of the present invention, the method further includes receiving a data signal and a reference voltage and outputting a data input signal, outputting the control signal, and receiving the data input signal and the writing even number data of the data input signal into a first latch in response to a rising edge of the output data signal and writing odd number data of the data input signal into a second latch in response to a falling edge of the output data strobe signal.